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1/18 august 2002 m27c512 512 kbit (64kb x8) uv eprom and otp eprom n 5v 10% supply voltage in read operation n access time: 45ns n low power acmoso consumption: active current 30ma standby current 100 m a n programming voltage: 12.75v 0.25v n programming times of around 6sec. n electronic signature manufacturer code: 20h device code: 3dh description the m27c512 is a 512 kbit eprom offered in the two ranges uv (ultra violet erase) and otp (one time programmable). it is ideally suited for applica- tions where fast turn-around and pattern experi- mentation are important requirements and is organized as 65,536 by 8 bits. the fdip28w (window ceramic frit-seal package) has transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. a new pattern can then be written to the device by following the programming procedure. for applications where the content is programmed only one time and erasure is not required, the m27c512 is offered in pdip28, plcc32 and tsop28 (8 x 13.4 mm) packages. figure 1. logic diagram ai00761b 16 q0-q7 v cc m27c512 gv pp v ss 8 a0-a15 e 1 28 28 1 fdip28w (f) pdip28 (b) plcc32 (c) tsop28 (n) 8 x 13.4 mm
m27c512 2/18 figure 2b. lcc connections ai00763 a13 a8 a10 q4 17 a0 nc q0 q1 q2 du q3 a6 a3 a2 a1 a5 a4 9 a14 a9 1 a15 a11 q6 a7 q7 32 du v cc m27c512 a12 nc q5 gv pp e 25 v ss figure 2a. dip connections a1 a0 q0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 q7 a14 a11 gv pp e q5 q1 q2 q3 v ss q4 q6 a12 a15 v cc ai00762 m27c512 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17 figure 2c. tsop connections a1 a0 q0 a5 a2 a4 a3 a9 a11 q7 a8 gv pp e q5 q1 q2 q3 q4 q6 a13 a14 a12 a6 a15 v cc a7 ai00764b m27c512 28 1 22 78 14 15 21 v ss a10 table 1. signal names a0-a15 address inputs q0-q7 data outputs e chip enable gv pp output enable / program supply v cc supply voltage v ss ground nc not connected internally du don't use
3/18 m27c512 table 2. absolute maximum ratings (1) note: 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum dc voltage on input or output is 0.5v with possible undershoot to 2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5v with possible overshoot to v cc +2v for a period less than 20ns. 3. depends on range. table 3. operating modes note: x = v ih or v il ,v id = 12v 0.5v. table 4. electronic signature symbol parameter value unit t a ambient operating temperature (3) 40 to 125 c t bias temperature under bias 50 to 125 c t stg storage temperature 65 to 150 c v io (2) input or output voltage (except a9) 2 to 7 v v cc supply voltage 2 to 7 v v a9 (2) a9 voltage 2 to 13.5 v v pp program supply voltage 2 to 14 v mode e gv pp a9 q7-q0 read v il v il x data out output disable v il v ih x hi-z program v il pulse v pp x data in program inhibit v ih v pp x hi-z standby v ih x x hi-z electronic signature v il v il v id codes identifie r a0 q7 q6 q5 q4 q3 q2 q1 q0 hex data manufacturer's code v il 00100000 20h device code v ih 00111101 3dh
m27c512 4/18 device operation the modes of operations of the m27c512 are list- ed in the operating modes table. a single power supply is required in the read mode. all inputs are ttl levels except for gv pp and 12v on a9 for electronic signature. read mode the m27c512 has two control functions, both of which must be logically active in order to obtain data at the outputs. chip enable (e) is the power control and should be used for device selection. output enable (g) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. assuming that the ad- dresses are stable, the address access time (t avqv ) is equal to the delay from e to output (t elqv ). data is available at the output after a delay of t glqv from the falling edge of g, assuming that e has been low and the addresses have been sta- ble for at least t avqv -t glqv . standby mode the m27c512 has a standby mode which reduces the active current from 30ma to 100 m athe m27c512 is placed in the standby mode by apply- ing a cmos high signal to the e input. when in the standby mode, the outputs are in a high imped- ance state, independent of the gv pp input. table 5. ac measurement conditions high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v figure 3. testing input output waveform ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 4. ac testing load circuit ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test table 6. capacitance (1) (t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test conditio n min max unit c in input capacitance v in =0v 6pf c out output capacitance v out =0v 12 pf
5/18 m27c512 table 7. read mode dc characteristics (1) (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c; v cc =5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v. table 8a. read mode ac characteristics (1) (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c; v cc =5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. 3. speed obtained with high speed ac measurement conditions. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 10 m a i lo output leakage current 0v v out v cc 10 m a i cc supply current e=v il ,g=v il , i out = 0ma, f = 5mhz 30 ma i cc1 supply current (standby) ttl e=v ih 1ma i cc2 supply current (standby) cmos e>v cc 0.2v 100 m a i pp program current v pp =v cc 10 m a v il input low voltage 0.3 0.8 v v ih (2) input high voltage 2 v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = 1ma 3.6 v output high voltage cmos i oh = 100 m av cc 0.7v v symbol alt parameter test condition m27c512 unit -45 (3) -60 -70 -80 min max min max min max min max t avqv t acc address valid to output valid e=v il ,g=v il 45 60 70 80 ns t elqv t ce chip enable low to output valid g=v il 45 60 70 80 ns t glqv t oe output enable low to output valid e=v il 25 30 35 40 ns t ehqz (2) t df chip enable high to output hi-z g=v il 0 25 0 25 0 30 0 30 ns t ghqz (2) t df output enable high to output hi-z e=v il 0 25 0 25 0 30 0 30 ns t axqx t oh address transition to output transition e=v il ,g=v il 0000ns
m27c512 6/18 figure 5. read mode ac waveforms ai00735b taxqx tehqz a0-a15 e g q0-q7 tavqv tghqz tglqv telqv valid hi-z valid table 8b. read mode ac characteristics (1) (t a = 0 to 70 c, 40 to 85 c or 40 to 125 c; v cc =5v 5% or 5v 10%; v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol alt parameter test condition m27c512 unit -90 -10 -12 -15/-20/-25 min max min max min max min max t avqv t acc address valid to output valid e=v il ,g=v il 90 100 120 150 ns t elqv t ce chip enable low to output valid g=v il 90 100 120 150 ns t glqv t oe output enable low to output valid e=v il 40 40 50 60 ns t ehqz (2) t df chip enable high to output hi-z g=v il 0 30 0 30 0 40 0 50 ns t ghqz (2) t df output enable high to output hi-z e=v il 0 30 0 30 0 40 0 50 ns t axqx t oh address transition to output transition e=v il ,g=v il 0000ns
7/18 m27c512 table 9. programming mode dc characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . symbol parameter test conditi on min max unit i li input leakage current v il v in v ih 10 m a i cc supply current 50 ma i pp program current e=v il 50 ma v il input low voltage 0.3 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh =1ma 3.6 v v id a9 voltage 11.5 12.5 v two line output control because eproms are usually used in larger memory arrays, the product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. the two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficient use of these two control lines, e should be decoded and used as the prima- ry device selecting function, while g should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the devices. the supply current, i cc , has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of e. the magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. the associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. it is recommended that a 0.1 m f ceram- ic capacitor be used on every device between v cc and v ss . this should be a high frequency capaci- tor of low inherent inductance and should be placed as close to the device as possible. in addi- tion, a 4.7 m f bulk electrolytic capacitor should be used between v cc and v ss for every eight devic- es. the bulk capacitor should be located near the power supply connection point.the purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of pcb traces.
m27c512 8/18 table 10. margin mode ac characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp. symbol alt parameter test condition min max unit t a9hvph t as9 v a9 high to v pp high 2 m s t vphel t vps v pp high to chip enable low 2 m s t a10heh t as10 v a10 high to chip enable high (set) 1 m s t a10leh t as10 v a10 low to chip enable high (reset) 1 m s t exa10x t ah10 chip enable transition to v a10 transition 1 m s t exvpx t vph chip enable transition to v pp transition 2 m s t vpxa9x t ah9 v pp transition to v a9 transition 2 m s figure 6. margin mode ac waveforms note: a8 high level = 5v; a9 high level = 12v. ai00736b ta9hvph tvpxa9x a8 e gv pp a10 set v cc tvphel ta10leh texvpx ta10heh a9 a10 reset texa10x
9/18 m27c512 table 11. programming mode ac characteristics (1) (t a =25 c; v cc = 6.25v 0.25v; v pp = 12.75v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol alt parameter test condition min max unit t avel t as address valid to chip enable low 2 m s t qvel t ds input valid to chip enable low 2 m s t vchel t vcs v cc high to chip enable low 2 m s t vphel t oes v pp high to chip enable low 2 m s t vplvph t prt v pp rise time 50 ns t eleh t pw chip enable program pulse width (initial) 95 105 m s t ehqx t dh chip enable high to input transition 2 m s t ehvpx t oeh chip enable high to v pp transition 2 m s t vplel t vr v pp low to chip enable low 2 m s t elqv t dv chip enable low to output valid 1 m s t ehqz (2) t dfp chip enable high to output hi-z 0 130 ns t ehax t ah chip enable high to address transition 0 ns e is pulsed to v il . the data to be programmed is applied to 8 bits in parallel to the data output pins. the levels required for the address and data in- puts are ttl. v cc is specified to be 6.25v 0.25v. the m27c512 can use presto iib pro- gramming algorithm that drastically reduces the programming time (typically less than 6 seconds). nevertheless to achieve compatibility with all pro- gramming equipments, presto programming algorithm can be used as well. programming when delivered (and after each erasure for uv eprom), all bits of the m27c512 are in the '1' state. data is introduced by selectively program- ming '0's into the desired bit locations. although only '0's will be programmed, both '1's and '0's can be present in the data word. the only way to change a '0' to a '1' is by die exposure to ultraviolet light (uv eprom). the m27c512 is in the pro- gramming mode when v pp input is at 12.75v and
m27c512 10/18 presto iib programming algorithm presto iib programming algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 6.5 seconds. this can be achieved with stmicroelectronics m27c512 due to several design innovations described in the m27c512 datasheet to improve programming effi- ciency and to provide adequate margin for reliabil- ity. before starting the programming the internal margin mode circuit is set in order to guarantee that each cell is programmed with enough margin. then a sequence of 100 m s program pulses are ap- plied to each byte until a correct verify occurs. no overprogram pulses are applied since the verify in margin mode provides the necessary margin. program inhibit programming of multiple m27c512s in parallel with different data is also easily accomplished. ex- cept for e, all like inputs including gv pp of the par- allel m27c512 may be common. a ttl low level pulse applied to a m27c512's e input, with v pp at 12.75v, will program that m27c512. a high level e input inhibits the other m27c512s from being pro- grammed. program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. the verify is accomplished with g at v il . data should be verified with t elqv after the falling edge of e. figure 7. programming and verify modes ac waveforms ai00737 tvplel program data in a0-a15 e gv pp q0-q7 data out tavel tqvel tvchel tvphel tehqx tehvpx teleh telqv tehax tehqz verify valid v cc figure 8. programming flowchart ai00738b n=0 last addr verify e = 100 m s pulse ++n =25 ++ addr v cc = 6.25v, v pp = 12.75v fail check all bytes 1st: v cc =6v 2nd: v cc = 4.2v yes no yes no yes no set margin mode reset margin mode
11/18 m27c512 electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the es mode is functional in the 25 c 5 c am- bient temperature range that is required when pro- gramming the m27c512. to activate the es mode, the programming equipment must force 11.5v to 12.5v on address line a9 of the m27c512. two identifier bytes may then be se- quenced from the device outputs by toggling ad- dress line a0 from v il to v ih . all other address lines must be held at v il during electronic signa- ture mode. byte 0 (a0 = v il ) represents the man- ufacturer code and byte 1 (a0 = v ih ) the device identifier code. for the stmicroelectronics m27c512, these two identifier bytes are given in table 4 and can be read-out on outputs q7 to q0. erasure operation (applies for uv eprom) the erasure characteristics of the m27c512 is such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 ?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 ? range. research shows that constant exposure to room level fluorescent lighting could erase a typical m27c512 in about 3 years, while it would take ap- proximately 1 week to cause erasure when ex- posed to direct sunlight. if the m27c512 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the m27c512 window to prevent unintentional erasure. the recommended erasure procedure for the m27c512 is exposure to short wave ultraviolet light which has wavelength 2537 ?. the integrated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 15 w-sec/cm 2 . the erasure time with this dos- age is approximately 15 to 20 minutes using an ul- traviolet lamp with 12000 m w/cm 2 power rating. the m27c512 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be removed before erasure.
m27c512 12/18 table 12. ordering information scheme note: 1. high speed, see ac characteristics section for further information. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. example: m27c512 -70 x c 1 tr device type m27 supply voltage c=5v device function 512 = 512 kbit (64kb x8) speed -45 (1) =45ns -60 = 60 ns -70 = 70 ns -80 = 80 ns -90 = 90 ns -10 = 100 ns -12 = 120 ns -15 = 150 ns -20 = 200 ns -25 = 250 ns v cc tolerance blank = 10% x= 5% package f = fdip28w b = pdip28 c = plcc32 n = tsop28: 8 x 13.4 mm temperature range 1=0to70 c 3 = 40 to 125 c 6=40to85 c optio ns x = additional burn-in tr = tape & reel packing
13/18 m27c512 table 13. revision history date version revision details november 1998 1.0 first issue 25-sep-2000 1.1 an620 reference removed 02-apr-2001 1.2 fdip28w mechanical dimensions changed (table 14) 29-aug-2002 1.3 package mechanical data clarified for pdip28 (table 15), plcc32 (table 16, figure 11) and tsop28 (table 17, figure 12)
m27c512 14/18 table 14. fdip28w - 28 pin ceramic frit-seal dip, with window, package mechanical data symbol millimeters inches typ min max typ min max a 5.72 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 0.177 b 0.41 0.56 0.016 0.022 b1 1.45 0.057 c 0.23 0.30 0.009 0.012 d 36.50 37.34 1.437 1.470 d2 33.02 1.300 e 15.24 0.600 e1 13.06 13.36 0.514 0.526 e 2.54 0.100 ea 14.99 0.590 eb 16.18 18.03 0.637 0.710 l 3.18 4.10 0.125 0.161 s 1.52 2.49 0.060 0.098 ? 7.11 0.280 a 4 11 4 11 n28 28 figure 9. fdip28w - 28 pin ceramic frit-seal dip, with window, package outline drawing is not to scale. fdipw-a a3 a1 a l b1 b e d s e1 e n 1 c a ea d2 ? eb a2
15/18 m27c512 table 15. pdip28 - 28 pin plastic dip, 600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a 4.445 0.1750 a1 0.630 0.0248 a2 3.810 3.050 4.570 0.1500 0.1201 0.1799 b 0.450 0.0177 b1 1.270 0.0500 c 0.230 0.310 0.0091 0.0122 d 36.830 36.580 37.080 1.4500 1.4402 1.4598 d2 33.020 1.3000 e 15.240 0.6000 e1 13.720 12.700 14.480 0.5402 0.5000 0.5701 e1 2.540 0.1000 ea 15.000 14.800 15.200 0.5906 0.5827 0.5984 eb 15.200 16.680 0.5984 0.6567 l 3.300 0.1299 s 1.78 2.08 0.070 0.082 a 0 10 0 10 n28 28 figure 10. pdip28 - 28 pin plastic dip, 600 mils width, package outline drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
m27c512 16/18 table 16. plcc32 - 32 lead plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 3.18 3.56 0.125 0.140 a1 1.53 2.41 0.060 0.095 a2 0.38 0.015 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 cp 0.10 0.004 d 12.32 12.57 0.485 0.495 d1 11.35 11.51 0.447 0.453 d2 4.78 5.66 0.188 0.223 d3 7.62 0.300 e 14.86 15.11 0.585 0.595 e1 13.89 14.05 0.547 0.553 e2 6.05 6.93 0.238 0.273 e3 10.16 0.400 e 1.27 0.050 f 0.00 0.13 0.000 0.005 r 0.89 0.035 n32 32 figure 11. plcc32 - 32 lead plastic leaded chip carrier, package outline drawing is not to scale. plcc-a d e3 e1 e 1n d1 d3 cp b e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 e2 d2 d2
17/18 m27c512 figure 12. tsop28 - 28 lead plastic thin small outline, 8 x 13.4 mm, package outline drawing is not to scale tsop-a d1 e 1n cp b e a2 a n/2 d die c l a1 a table 17. tsop28 - 28 lead plastic thin small outline, 8 x 13.4 mm, package mechanical data millimeters inches symbol typ min max typ min max a 1.250 0.0492 a1 0.200 0.0079 a2 0.950 1.150 0.0374 0.0453 b 0.170 0.270 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d 13.200 13.600 0.5197 0.5354 d1 11.700 11.900 0.4606 0.4685 e 0.550 0.0217 e 7.900 8.100 0.3110 0.3189 l 0.500 0.700 0.0197 0.0276 a 0 5 0 5 n28 28
m27c512 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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